1. Technical Field
The present invention relates to a three-dimensional system-on-chip structure formed by stacking multiple chip modules. More particularly, the present invention relates to a three-dimensional system-on-chip structure which is formed by stacking a plurality of chip modules and applicable to system-on-chips.
2. Description of Related Art
A system-on-chip (SoC) refers to an integrated chip on a system level. In particular, a system-on-chip may include a computational element (e.g., a microprocessor, a digital signal processor, an image processor, etc.) as well as a memory, a logic circuit, an input/output circuit, and other connection circuits. In a nutshell, a system-on-chip is a single chip integrated with IC components which have different functions and are otherwise scattered in different chips. Therefore, a system-on-chip can be regarded as a single system having multiple functions.
At the front-end design stage of a SoC development process, system developers plan the desired components and architectures. These components and architectures may be designed by the system developers themselves or provided by a third party. In either case, however, it is the system developers who are responsible for manufacturing and verifying the finished products at the back-end fabrication and verification stages.
While system developers may incorporate the silicon intellectual property (SIP) of external design teams during the design stage, the remaining part of the development process, particularly fabrication and verification, cannot be outsourced. Although such a development process provides system developers with a high degree of autonomy and allows them to optimize product design at the latter stages, the costs of man power and time are lofty. Therefore, if the design stage can be extended into and integrated with fabrication and verification, that is, if certain components of a system-on-chip are pre-fabricated and verified products, then system developers are allowed to focus only on the design, fabrication, and verification of those components with the additional extended functions. Thus, the time required for developing and testing the system-on-chip is significantly shortened, and design errors minimized, thereby lowering the development costs.
Moreover, as consumers strongly prefer electronic products featuring compactness, if the volume of system-on-chips is effectively reduced, the finished electronic products can be downsized to satisfy consumers.